T2.5 Model and Simulation
- TCAD & EDA Tools and automation for assessing the influence of substrate parameters on technology performance (SILVACO)
- Methodology and simulations for analysing the wafer impact on analog and RF performance (SILVACO, UCL, CEA, SOITEC)
- Modelling and silicon correlation (CEA, UCL)
In this task, we will model the existing wafer product portfolio (Gen 1.1, eSoC.2, eSoC.3) and quantify the performance gain attached to each generation. The goal will be to map each wafer generation to the most relevant market segment and understand if there is a need in future for advanced wafer generation or specific wafer grade for a given market segment.
The challenges consist of understanding wafer process manufacturing, model corresponding process recipes and correlate those recipes with the quality of the substrate (film thickness, uniformity roughness, dislocation, traps, strain, ...) and finally transfer the simulation results into a device simulator to assess device performance.
The challenges will be:
Identify key wafer substrate processing parameters and their impact on the substrate quality (defects)
Develop a model linking wafer process parameters and defect in the substrate.
Implement the model developed in section 1 in Silvaco device simulator.
Use the model to assess device performance as a function of the substrate quality.
Link the substrate properties to the MOSFET and integrated passive components thanks to compact modelling
Provide guideline for SOI substrate definition for advanced FDSOI technologies
Characterization and model correlation through Si vs CAD for each wafer generation in close collaboration with T2.4 (whenever available).