WP3 - IP Platform

The objectives of Work Package 3 are:

O3.1: To design the key features & innovative IP (circuit design, verification, manufacturing and validation effort) in order to enable from the ground up the necessary advanced applications in various FDSOI technology flavors (28nm, 22FDX, 18nm FDSOI).

O3.2: to clusters all of the soft and hard IP/PHY/Front-End design activities to leverage synergies between circuit designing partners, which are working towards providing generic or dedicated and self-contained circuit building blocks.

O3.3: to develop innovative EDA methodologies to improve the efficiency, productivity and quality of implementation of silicon IP through machine-learning, automatic synthesis and improvement of optimization algorithms.

O3.4: to act as semiconductor IP factory to build up necessary hard and soft sub-components (IP cores with or without supporting side-files later needed for chip integration) for the requirements of the designed IC components in Work Package 4.

At project level, the common system requirements are analysed at User Requirements Level (WP1) and broken down into Demonstrator and Component requirements in WP5 and WP4, respectively.