Definition of the requirements of the IP platform

The IP platform is the underlying foundation for the SOI components, providing a library of pre-designed functional blocks that can be used to build new circuits and systems. This Task aims to define the requirements for the IP platform, also using the results from Task 1.2, thus the requirements from the IP platform.

The WP3 is composed of different tasks with concurrent activities and timeline, therefore the requirements for each task are defined separately in independent deliverables.

IMST will contribute concerning the following points:

• CMOS RF IP selection (low power, > 100 GHz)
• IP Requirement specifications for 22nm and beyond telecommunication/radar applications (PLL, PA, ..)
• Requirements on versatility for down (and up?) scaling and application retargeting
• EDA bottlenecks and required flow extensions to achieve required performance, flexibility and securing reliability
• TAS will provide some specifications for the challenging future spatial communication systems with a particular focus on RF requirements, Analog to Digital Interface and Digital Signal Processing. A particular attention will be paid to the radiation hardening requirements.
• UTIA will contribute in the specification of HW IPs, SW, test framework and use case", in particular:
• Specification of HW IPs for AI inference for SOI
• Specification of HW IPs for GP SIMD DPU (FP32/FP16) for SOI
• Specification of SW and test framework