Electrostatic and mobility enhancement

Different techniques will be studied to improve the electrostatic and mobility properties of transistors for reduced gate length transistors.

We will work on the development of

• (1) specific SOI substrates(sSOI) able to generate global constraints on transistors NMOS device couple with study to relax the strain locally for PMOS devices. (CEA; SOITEC)
• (2) Local strain boosters for both NFET and PFET. Local strain in the NFETs channel through BOX creep, STRASS technique and for PFETs, their performances will benefit from in plane stressors induced by higher germanium content in the source and drain area. A specific study on plasma immersion ion implantation (PIII) will be carried out by IBS to demonstrate the benefits of this tool for simplifying the local strain manufacturing process. (CEA; IBS)
• (3) Electrostatic booster will be used by thinning down the channel without impacting the access resistance or the epitaxy yield or by access reduction thanks to new epi S/D coupled with optimized activation anneal and salicidation steps. The IBS implant equipment (PIII) will be used to evaluate the possible gains in terms of contact doping and silicide structure. (CEA, IBS)
• (4) the development of integration schemes to enhance strain-transfer efficiency through release of mechanical strained boundaries and test of different materials for with different stress level for CESL