Embedded Non Volatile Memories enhancement (PCM)

CEA will work on the three main challenges that we have described in the ambition, namely:

(1)-The raising of the PCM cell from 'M0' to 'true' BEOL

Investigate the effects of the PCM introduction into the BEOL of the fabrication of FDSOI 28 nm, on the device morphology and performances. Evaluate the device scaling along the z-axis, in particular optimizing the thickness of the PCM layer and the thermal barrier between PCM and top electrode;

(2)-The reduction of the 'drift': a reliability challenge

New GeXSbYTeZ stoichiometries will be investigated, benchmarking compositions with low and high Sb/Te ratio (Y/Z). Together with the doping by ion implantation or co-sputtering, they will be designed to improve the crystalline morphology of the SET state of the device to reduce/hinder the drift phenomenon and improve the memory window (i.e. lower BER);

(3)-Preparing PCM technology for IMC and AI

The effects of the shrink of the cell critical dimension will be investigated, and different materials. benchmarked wrt. their reliability; Assessment of MLC/analog behaviour reliability in state of the art devices integrated in the BEOL of the fabrication: possible IMC architectures will be proposed and their performances analysed wrt. devices electrical results.