High-performance RF

This task encompasses designs for mm-wave building blocks for a frequency >= 60 GHz (ISM band, FMCW radar, W-band/D-band and in general sub-THz) for sensing and communication applications. It is split to three distinctive subtasks.

Challenges addressed:

• Open-loop topology for wideband chirp generation
• 'Electronic' crystal replacing quartz, saving 2 package pins
• Beyond SotA IP3, NF, efficiency and system integration for W-band with 28 FDSOI
• Establish a relation between circuit performance and technological parameters (substrate characteristics, FEOL FOMs, BEOL FOMS)
• Develop a systematic method based on convex optimization for RF circuit design
• Task 3.2.1 Radar IP (Bosch, IMS, )

Bosch will develop the IP design targeting a mm-wave Integrated Circuit for automotive radar. In the future, automotive radars will observing the entire surrounding of the vehicle to monitor other vehicles and road users. The next generation automotive radar should provide increased interference robustness, more flexibility and accuracy. To achieve this, the bandwidth will be increased and the transmitter and receiver will be digital modulated instead of analog.

Bosch will design a highly integrated and optimized IP for a System on Chip. The IP will enable object detection based on radio waves to determine the range, angle, or velocity of objects. The novel high accuracy target specifications will enable objects detection within a larger area. The optimized IP will be highly miniaturized and integrated using GF 22FDX.

IMS will work on three designs of frequency generation units (FGU) below:

• an 80GHz FMCW radar FGU to provide high-resolution radar detection as required for autonomous car driving. This approach is needed for high-resolution radars dedicated to autonomous driving. This unit will provide fast, broadband chirp generation from 76 to 80 GHz, using an open-loop modulation scheme. This will ensure minimal power consumption. Frequency accuracy will be controlled by a replica oscillator, combining the robustness of closed-loop and the agility of open-loop topologies.
• a 60GHz low-power radar FGU for in-cabin applications (kid detection, intrusion detection, and so on). The topology of this unit will be based on an electronic crystal instead of a real one, and an inductorless oscillator. Both these approaches will allow a significant silicon footprint reduction, further reducing the cost of the device. To select the best architecture, the work will start with a benchmark between impulse-radio radars and duty-cycled radars. the ultra-low power consumption behaviour will pave the way to continuous time of operation, even when the vehicle is parked.
• an ultra-low power FGU for IoT dedicated to connectivity (inductorless and digitally inspired PLL). will study, design and characterize an IP consisting of a wideband phase-locked loop in P18RF, the 18nm FDSOI CMOS technology from STMicroelectronics. To fully take advantage of the high integration this technology offers, the here-discussed synthesizer will have a digitally-inspired topology with a digitally-controlled ring oscillator, a novel time-to-digital converter, and a digital loop filter. This loop will have a wideband behaviour, to allow oscillator phase noise clean-up. In doing so, a dirty (noisy) oscillator should be brought into play when still respecting the Bluetooth Low Energy standard requirements.
• Task 3.2.2 W-band Communication IP (SIAE, UNICAL)

SIAE activities will be focused on the System analysis, design, development and manufacturing of the key building blocks of a W- band Front End Module (FEM), designed by using the 28nm FDSOI technology provided by STMicroelectronics. It will enable high volume production of a high-capacity Radio for Point-to-Point (PtP) or multi-Point-to Point (MPtP) applications in W-band (92 GHz – 114 GHz). The project aims to overcome in terms of linearity (IP3), NF, efficiency and System integration the solutions currently available in W-band. The proposed solution will take advantage of the characteristics offered by 28nm FDSOI in terms of isolation, level of integration and RF performances.

UNICAL activity will be mainly oriented to the development of a Butler matrix (BM) monolithically integrated in 28nm FD-SOI technology provided by STMicroelectronics to be employed on the W- band Front End Module (FEM). A BM is a passive beam-forming network that can be used in multibeam or switched beam antenna architecture. It is a passive device that divides and combines signals so that multiple beams can be generated without requiring a phased array implementation.

• Task 3.2.3 Disruptive analog/RF Transceiver IP (IMEC, ETHZ, CEA, ECL, ARGUS, UCL)

IMEC will primarily use 22FDX with a possible extension towards 18nm FDSOI for comparison and benchmarking. The objective of IMEC is to explore the design possibilities offered by the FDSOI technologies and push the performance boundaries at circuit level in terms of efficiency, operation frequency and integration density. IMEC will perform devices characterization and VCO circuit design, validation and benchmarking in view of strategic roadmapping. IMEC will feedback their findings and learning towards the earlier work packages for technology and PDK enhancements, and the obtained circuit performance will be used in WP4 to estimate the chip/system performance for certain use cases and/or applications.

ARGUS team will be responsible for one IPs using CMOS SOI technologies: Ku-band (12-18 GHz) and Ka-band (26.5-40 GHz) RF Beamformers including Driver Circuits. Proposed performance specifications: >10dBm Peak Pout and <4dB NF, Phase Shifters with 360-degrees phase shift and <15dB insertion loss, and 8:1 Beamformers. We intend to design mainly in Globalfoundries 22FDX technology, whose MPW runs regularly in recent years.

CEA intend to push the evaluation using 28 FDSOI, 22FDX and 18 FDSOI for comparison and benchmarking. The objective of CEA is to setup a rigorous evaluation method of the capacity of the technology. Thanks to this approach, it will be possible to achieve a fine technology comparison and to provide some feedback for the technology team to better adjust the future technologies. CEA will perform building blocks design and characterization and analog low pass filter design, validation and benchmarking. CEA will also feedback their findings and learning towards the earlier work packages for technology and PDK enhancements, and the obtained circuit performance will be used in WP4 to estimate the chip/system performance for certain use cases and/or applications.

ECL aims to develop a systematic approach based on convex optimization for the analysis and design of analog/RF basic cells, with a particular focus on the design of analog filters based on gmC/Id models. Thanks to this promising approach, it is expected to shorten the design flow and to tackle more complex circuit design problems (in terms of specifications or models used) compared to the traditional simulation-based methods. Based on this result, and in close collaboration with CEA, ECL plans to build up rigorous methods for assessing and improving the performance of current and future technologies.

ETHZ team will be responsible for two sets of IPs using CMOS SOI technologies.

(1) Ultra-Compact D-band Frontend Circuits and Array. Proposed performance specifications: PA with >10dBm Peak Pout and > 8% peak PAE, LNA with <5.5dB NF, Phase Shifters with 360-degrees phase shift and <15dB insertion loss. The goal is to make the entire array design be on-grid and matching the lamda/2*lamda/2 2D array.

(2) Q-band (33-50GHz) Frontend Circuits. Proposed performance specifications: PA with >10dBm Peak Pout and > 15% Peak PAE, LNAs with <4dB NF, and Phase Shifters with 360-degrees phase shift and <15dB insertion loss.

UCL aims at designing key building blocks (LNA, PA, switch, ...) for highly integrated sub-THz applications using FDSOI technology. Priority will be given to D-band applications, higher frequency ranges will also be investigated. The study will focus on evaluating the best performance achievable from the technology and attempt to establish a close link between circuit performance and technological parameters (substrate characteristics, FEOL FOMs, BEOL FOMS). Focus will also be given to understanding the benefits and constraints provided by the back gate for sub-THz circuits. This part of our study will lead to close interactions with the UCL characterization activities planned in WP2. The study will also focus on determining new and innovative circuit topologies for sub-THz circuits on FDSOI, which will fully account for the constraints and benefits of the FDSOI technology. The fabricated circuits will be characterized at UCL (D-band small signal measurements) or at partner's facilities (IMS, CEA, ...). The circuits will be benchmarked against other technologies and published data.